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32K x 8 Radiation Hardened Static RAM - 5 V
Features
167A690 182A934
Product Description
Other * Read/Write Cycle Times 30 ns (-55 C to 125C) * SMD Number 5962H92153 * Asynchronous Operation * CMOS or TTL Compatible I/O * Single 5 V 10% Power Supply * Low Operating Power * Packaging Options * 36-Lead Flat Pack (0.630" x 0.650") * 28-Lead DIP, MIL-STD-1835, CDIP2-T28
Radiation * Fabricated with Bulk CMOS 0.8 m Process * Total Dose Hardness through 1x106 rad(Si) * Neutron Hardness through 1x1014 N/cm2 * Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s * Soft Error Rate of < 1x10-11 Upsets/Bit-Day * Dose Rate Survivability through 1x1012 rad(Si)/s * Latchup Free
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General Description
The 32K x 8 radiation hardened static RAM is a high performance, low power device designed and fabricated in 0.8 m Radiation Hardened Complementary Metal Oxide Semiconductor (RHCMOS) technology. BAE SYSTEMS' device is designed for radiation environments using industry standard functionality. The memory can be personalized for either CMOS or Transistor Transistor Logic (TTL) input receivers. The SRAM operates over the full military temperature range and requires a single 5 V 10% power supply. Power consumption is typically less than 20 mW/MHz in operation, and less than 10 mW in the low power disabled mode. The SRAM read operation is fully asynchronous, with an associated typical access time of 20 nanoseconds. BAE SYSTEMS' bulk CMOS technology achieves radiation hardening via a combination of process technology enhancements and specific circuit improvements.
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BAE SYSTEMS * 9300 Wellington Road * Manassas, Virginia 20110-4122
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Functional Diagram
*** A:11 32,768 x 8 Memory Array *** Column Decoder Data Input/Output
Row Decoder
E S
W
G
A:4 DQ:8
Signal Definitions
A: 0-14
- Address input pins that select a particular eight-bit word within the memory array. - Bi-directional data pins that serve as data outputs during a read operation and as data inputs during a write operation. - Negative chip select, when at a low level, allows normal read or write operation. When at a high level, S forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables the data input buffers only. If this signal is not used, it must be connected to GND.
W
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- Negative write enable, when at a low level, activates a write operation and holds the data output drivers in a high impedance state. When at a high level, W allows normal read operation. - Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by S, W, and E. If this signal is not used it must be connected to GND. - Chip enable, when at a high level allows normal operation. When at a low level, E forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the S input buffer. If this signal is not used, it must be connected to VDD.
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G
S
E
Truth Table
Inputs(1),(2) E (4) High High X Low S Low Low High X W Low High X X G X Low X X I/O Data-In Data-Out High-Z High-Z Notes: Power Active Active Standby Standby 1) VIN for don't care (X) inputs = VIL or VIH. 2) When G = high, I/O is high-Z. 3) To dissipate the minimum amount of standby power when in standby mode: S= VDD and E = GND. All other input levels may float. 4) E is tied high internally to the chip for the 28-DIP package.
Mode Write Read Standby Standby(3)
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Absolute Maximum Ratings
Applied Conditions(1) Storage Temperature Range (Ambient) Operating Temperature Range (TCASE) Positive Supply Voltage Input Voltage(2) Output Voltage(2) Power Dissipation(3) Lead Temperature (Soldering 5 sec) Electrostatic Discharge Sensitivity(4)
Notes:
Minimum -65C -55C -0.5 V -0.5 V -0.5 V
Maximum +150C +125C +7.0 V VDD+ 0.5 V VDD+ 0.5 V
2.0 W +250C (Class II)
1) Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. All voltages are with reference to the module ground leads. 2) Maximum applied voltage shall not exceed +7.0 V. 3) Guaranteed by design; not tested. 4) Class as defined in MIL-STD-883, Method 3015.
Recommended Operating Conditions
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Symbol VDD GND TC VIL VIH Parameters(1) Minimum Supply Voltage +4.5 .com Supply Voltage Reference Case Temperature Input Logic "Low" - CMOS Input Logic "Low" - TTL Input Logic "High" - CMOS Input Logic "High" - TTL
Note:
Maximum +5.5 0.0 +125 +1.5 +0.8 VDD VDD
Units Volt Volt Celsius Volt Volt
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0.0 -55 0.0 0.0 +3.5 +2.0
1)All voltages referenced to GND.
Power Sequencing
The substrate of this module is connected directly to Ground. Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents: * Power-Up Sequence: GND, VDD, Inputs * Power-Down Sequence: Inputs, VDD, GND
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DC Electrical Characteristics
Limits Minimum Maximum 180 130 2.0 1.2 2.0 2.0 1.2 2.0 1.0 0.4 1.0 4.2 VDD - 0.5 V 0.4 0.05 2.5 3.5 2.0 1.5 0.8 -5 -10 5 10 4
Test
Symbol
Test Conditions(1) F = FMAX = 1/tAVAV(min) S = VIL = GND E = VIH = VDD No Output Load F = FMAX = 1/tAVAV(min) S = VIH = VDD E = VIL= GND F = FMAX = 1/tAVAV(min) S = VIH = VDD E = VIL= GND VDD= 2.5 V IOH= -4 mA IOH = -200 A IOL= 8 mA IOL = 200 A VDD = VDR
Device Type X3X X4X X6X X3X X4X X6X X3X X4X X6X X3X X4X X6X All All All CMOS TTL CMOS
Units mA mA mA mA mA mA mA mA mA mA mA V V V V V A A pF
Supply Current (Cycling Selected)
IDD1
Supply Current (Cycling De-Selected) Supply Current (Standby)
IDD2
IDD3
Data Retention Current
IDR
High Level Output Voltage Low Level Output Voltage Data Retention Voltage High Level Input Voltage
VOH VOL VDR VIH VIL IILK IOLK (2)
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Low Level Input Voltage Input Leakage Output Leakage Cin
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TTL .com 0 V VIN 5.5 V 0 V VOUT 5.5 V By Design/ Verified By Characterization By Design/ Verified By Characterization All All All
Cout
(2)
All
7
pF
Note: 1) Typical operating conditions: VDD = 5.0V; TA = 25 C, pre-radiation. -55C Tcase +125C; 4.5 V VDD 5.5 V; unless otherwise specified. 2) The worst case timing sequence of tWLZQ + tDUWH + tWHWL = tAVAV.
Output Load Circuit
300 10% 2.8V
50 pF + 10%
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Read Cycle AC Timing Characteristics(1)
Minimum or Maximum Minimum Maximum Minimum Maximum Minimum Maximum Maximum Minimum Maximum Maximum Minimum Maximum Worst Case By Speed -30 -40 -60 30 30 5 30 3 CMOS - 10 TTL - 12 30 3 40 40 5 40 3 15 40 3 60 60 5 60 3 15 60 3 15 15 3 15
Test Read Cycle Time Address Access Time Output Hold After Address Change Chip Select Access Time Chip Select to Output Active Chip Select to Output Disable Chip Enable Access Time Chip Enable to Output Active Chip Disable to Output Disable Output Enable Access Time Output Enable to Output Active Output Enable to Output Disable
Symbol tAVAV tAVQV tAXQX tSLQV tSLQX tSHQZ tEHQV tEHQX tELQZ tGLQV tGLQX tGHQZ
Units ns ns ns ns ns ns ns ns ns ns ns ns
CMOS - 10 15 TTL - 12 CMOS - 12 CMOS - 15 TTL - 18 TTL - 15 3 CMOS - 10 TTL - 12 3 15
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Note:
1)Test conditions: input switching levels VIL/VIH = 0.5 V/VDD -0.5 V (CMOS), VIL/VIH = 0 V/3 V (TTL), input rise and fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics .com table, capacitive output loading CL = 50 pF. For CL > 50 pF, derate access times by 0.02 ns/pF (typical). -55 C Tcase +125C; 4.5 V VDD 5.5 V; unless otherwise specified.
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Read Cycle Timing Diagram
tAVAV
Address
Valid Address
tAVQV tSLQV
S
tAXQX
tSLQX tEHQV
E
tSHQZ
tEHQX tGLQV
G
tELQZ
tGLQX
Data Out
tSHQZ
Valid Data
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Write Cycle AC Timing Characteristics(1)
Test Write Cycle Time Write Pulse Width Chip Select to End of Write Data Setup to End of Write Address Setup to End of Write Data Hold After End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write Write Pulse Width Access Time Chip Enable to End of Write Address Hold After End of Write
Note:
Symbol tAVAV tWLWH tSLWH tDVWH tAVWH tWHDX tAVWL tWHAX tWLQZ tWHQX tWHWL tEHWH tELWH
Minimum or Maximum Minimum Minimum Minimum Minimum Minimum Minimum Minimum Minimum Maximum Minimum Minimum Minimum Minimum
Worst Case By Speed -30 -40 -60 35 30 30 25 30 3 0 0 12 1 5 30 0 40 35 35 30 35 3 0 0 15 1 5 35 0 40 55 55 40 55 5 0 0 15 3 5 55 0
Units ns ns ns ns ns ns ns ns ns ns ns ns ns
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1) Test conditions: input switching levels VIL/VIH = 0.5 V/VDD - 0.5 V (CMOS), VIL/VIH = 0 V/3 V (TTL), input rise and fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading = 50 pF. -55C Tcase +125C; 4.5 V VDD 5.5 V; unless otherwise specified.
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Write Cycle Timing Diagram
tAVAV
Address
Valid Address tAVWH tSLWH tWHAX
S
E
tEHWH tWLWH
W
tAVWL
Data Out
tWLQZ High Impedance tDVWH
tWHWL tWHQX
High Impedance
tWHDX
Data In
High Impedance
Valid Data
High Impedance
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Dynamic Electrical Characteristics
Read Cycle The RAM is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (S), or chip enable (E) (refer to Read Cycle Timing diagram). To perform a valid read operation, both chip select and output enable (G) must be low and chip enable and write enable (W) must be high. The output drivers can be controlled independently by the G signal. Consecutive read cycles can be executed with S held continuously low, and with E held continuously high, and toggling the addresses. For an address-activated read cycle, S and E must be valid prior to or coincident with the activating address edge transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid tAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is tAVQV . When the RAM is operated at the minimum address-activated read cycle time, the data outputs will remain valid on the RAM I/O until tAXQX time following the next sequential address transition.
Write Cycle The write operation is synchronous with respect to the address bits, and control is governed by write enable (W), chip select (S), or chip enable (E) edge transitions (refer to Write Cycle Timing diagrams). To perform a write operation, both W and S must be low, and E must be high. Consecutive write cycles can be performed with W or S held continuously low, or E held continuously high. At least one of the control signals must transition to the opposite state between consecutive write operations. The write mode can be controlled via three different control signals: W, S, and E. All three modes of control are similar except the S and E controlled modes actually disable the RAM during the write recovery pulse. Only the W controlled mode is shown in the table and diagram on the previous page for simplicity. However, each mode of control provides the same write cycle timing characteristics. Thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low.
To control a read cycle with S, all addresses and E must be valid prior to or coincident with the enabling S edge transition. Address or E edge transitions can occur later than the specified setup times to S; however, the valid data To write data into the RAM, W and S must be held low access time will be delayed. Any address edge transition, and E must be held high for at least tWLWH /tSLSH /tEHEL time. that occurs during the time when S is low, will initiate a new t4U.com t4U.com DataShee read access, and data outputs will not become valid until Any amount of edge skew between the signals can be DataS tAVQV time following the address edge transition. Data tolerated and any one of the control signals can initiate or .com outputs will enter a high impedance state tSHQZ time terminate the write operation. For consecutive write following a disabling S edge transition. operations, write pulses must be separated by the To control a read cycle with E, all addresses and S must be valid prior to or coincident with the enabling E edge transition. Address or S edge transitions can occur later than the specified setup times to E; however, the valid data access time will be delayed. Any address edge transition that occurs during the time when E is high will initiate a new read access, and data outputs will not become valid until tAVQV time following the address edge transition. Data outputs will enter a high impedance state tELQZ time following a disabling E edge transition.
minimum specified tWHWL /tSHSL /tELEH time. Address inputs must be valid at least tAVWL /tAVSL /tAVEH time before the enabling W/S/E edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of tDVWH /tDVSH /tDVEL, and an address valid to end of write time of tAVWH /tAVSH /tAVEL also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling W/S/E edge transition must be a minimum of tWHAX /tSHAX /tELAX time and tWHDX /tSHDX /tELDX time, respectively. The minimum write cycle time is tAVAV.
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Radiation Characteristics
Total Ionizing Radiation Dose The SRAM will meet all stated functional and electrical specifications over the entire operating temperature range after a total ionizing radiation dose of 1x106 rad(Si). All electrical and timing performance parameters will remain within specifications after rebound at VDD = 5.5 V and T = 125C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and RAM product using 10 keV X-ray and Co60 radiation sources. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a dose rate of 1x105 rad(Si)/min at T = 25C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. Transient Pulse Ionizing Radiation The SRAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse of 50 ns duration up to 1x109 rad(Si)/s, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation is 10%), stiffening capacitance can be placed on the package between the package (chip) VDD and GND with the inductance between the package (chip) and stiffening capacitance kept to a minimum. If there are no operatethrough or valid stored data requirements, typical de-coupling capacitors should be mounted on the circuit board as close as t4U.com possible to each device. t4U.com The SRAM will meet any functional or electrical specification after exposure to a radiation pulse of 50 ns duration up to 1x1012 rad(Si)/s, when applied under recommended operating conditions. Note that the current conducted during the pulse by the RAM inputs, outputs, and power supply may significantly exceed the normal operating levels. The application design must accommodate these effects. Neutron Radiation The SRAM will meet any functional or timing specification after a total neutron fluence of up to 1x1014 cm-2 applied under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV. Soft Error Rate The SRAM has a soft error rate (SER) performance of <1x10-11 upsets/bit-day, under recommended operating conditions. This hardness level is defined by the Adams 90% worst case cosmic ray environment. Latchup The SRAM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions.
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Radiation Hardness Ratings (1),(2)
Symbol
Characteristics
Conditions
Minimum
Maximum
Units
RTD RPRU RS SEU1 SEU2 RNF SEL
Total Dose Prompt Dose Upset Survivability Single Event Upset(3) Single Event Upset (3) Neutron Fluence Single Event Induced Latchup
MIL-STD-883, TM 1019.5 Condition A 20 - 50 ns Pulse Width Tcase = 25C and 125C 20 - 50 ns Pulse Width Tcase = 125C -55C Tcase 80C -55C Tcase 125C
1E + 06 1E + 09 1E + 12 1E - 11 1E - 10 1E + 14
rad(Si) rad(Si)/s rad(Si)/s Upsets/Bit-Day Upsets/Bit-Day N/cm 2 Immune (4)
-55C Tcase 125C VDD = 5.5 V
Notes: 1) Measured at room temperature unless otherwise stated. Verification test per TRB approved test plan. 2) Device electrical characteristics are guaranteed for post irradiation levels at 25C. 3) 90% worst case particle environment, geosynchronous orbit, 0.025'' of aluminum shielding. Specification set using the CREME code upset rate calculation method with a 2 m epi thickness. 4) Immune for LET 120 MeV/mg/cm 2.
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Tester AC Timing Characteristics
TTL I/O Configuration
CMOS I/O Configuration
Input Levels*
3V
. . . . . . . . . . . . . . . 1.5 V 0V........
VDD- 0.5 V
. . . . . . . . . . . . . V /2 DD 0.5 V . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 1.5 V
Output Sense Levels
. . . . . . . . . . . . . V /2 DD . . . . . VDD- 0.4 V High Z . . . . . 0.4 V 3.4 V . . . . 2.4 V . . . .
High Z = 2.9 V
. . . . . VDD- 0.4 V High Z . . . . . 0.4 V 3.4 V . . . . 2.4 V . . . .
High Z = 2.9 V
High Z
High Z
*Input rise and fall times <5 ns
t4U.com t4U.com Radiation Hardness Assurance
BAE SYSTEMS provides a superior quality level of radiation hardness assurance for our products. The excellent product quality is sustained via the use of our qualified QML operation which requires process control with statistical process control, radiation hardness assurance procedures and a rigid computer controlled manufacturing operation monitoring and tracking system. The BAE SYSTEMS technology is built with resistance to radiation effects. Our product is designed to exhibit < 1e -11 fails/bit-day in a 90% worst case geosynchronous orbit under worst case operating conditions. Total dose hardness is assured by irradiating test structures on every lot and total dose exposure with Cobalt 60 testing performed quarterly on TCI lots to assure the product is meeting the QML radiation hardness requirements.
Reliability
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BAE SYSTEMS' reliability starts with an overall product assurance system that utilizes a quality system involving all employees including operators, process engineers and product assurance personnel. An extensive wafer lot acceptance methodology, using in-line electrical data as well as physical data, assures product quality prior to assembly. A continuous reliability monitoring program evaluates every lot at the wafer level, utilizing test structures as well as product testing. Test structures are placed on every wafer, allowing correlation and checks within-wafer, wafer-to-wafer, and from lot-to-lot. Reliability attributes of the CMOS process are characterized by testing both irradiated and non-irradiated test structures. The evaluations allow design model and process changes to be incorporated for specific failure mechanisms, i.e., hot carriers, electromigration, and time dependent dielectric breakdown. These enhancements to the operation create a more reliable product. The process reliability is further enhanced by accelerated dynamic life tests of both irradiated and non-irradiated test structures. Screening and testing procedures from the customer are followed to qualify the product. A final periodic verification of the quality and reliability of the product is validated by a TCI (Technology Conformance Inspection).
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Screening Levels
BAE SYSTEMS has two QML screen levels (Q and V) to meet full compliant space applications. For limited performance and evaluation situations, BAE SYSTEMS offers an engineering screen level.
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Standard Screening Procedure
QML Level Q V
Flow
Comments
Wafer Lot Acceptance Serialization Destructive Bond Pull Internal Visual Temperature Cycle Constant Acceleration PIND Radiography Electrical Test Dynamic Burn-In Electrical Test Static Burn-In Final Electrical PDA Fine and Gross Leak External Visual
X X Sample X X X X X X
X X Sample X X X X X X X X X X X X X
Alternate Method Used Die Traceability MIL-STD-883, TM 2010
5.5 V, 125C, 144 Hours Meets Group A < 5% Fallout MIL-STD-883, TM 2009
X X X X
Burn-In Circuit
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Stress Methodology
There are two methods of burn-in defined. For "Static" burn-in, .com all possible addresses are written with a logic "1" for half of the burn-in duration and a logic "0" for the remaining half. For "Dynamic" burn-in, all possible addresses are written with alternating high and low data. All I/O pins specified in the static and dynamic burn-in pin lists are driven through individual series resistors (1.6K 10%). The burn-in circuit diagram is shown at right. Voltage Levels * Vin(0): 0.0 V to + 0.4 V - VIL = Low level for all programmed signals *Vin(1): + 5.4 V to + 6.0 V - VIH = High level for all programmed signals * V1: + 5.5 V (-0% / +10%) - All VDD pins are tied to this level *Vsx: Float or GND - All GND pins are tied to this level S E W G A0 V1 C1 C1 = 0.1 F (10%) R = 1.6K (10%)
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R R R R R
* * * 32K x 8 SRAM
R
* * * * *
DQ0 DIN DQ7
R
A14
R
Pin Listing The dynamic burn-in pin listing is shown at right. F = square wave, 100 KHz to 1.0 MHz.
Input A0 A1 A2 A3 A4
Signal F/2 F/4 F/8 F/16 F/32
Input A5 A6 A7 A8 A9
Signal F/64 F/128 F/256 F/512 F/1024
Input A10 A11 A12 A13 A14
Signal F/2048 F/4096 F/8192 F/16384 F/32768
Input W DIN S G E
Signal F/65536 F/131072 F VIL VIH
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Packaging
The 32K x 8 SRAM is offered in a custom 36-lead FP, 36-lead FPP or standard 28-lead DIP. All packages are constructed of multilayer ceramic (AI2O3) and feature internal power and ground planes. The FP also features a non-conductive ceramic tie bar on the lead frame. The purpose of the tie bar is to allow electrical testing of the device, while preserving the lead integrity during shipping and handling, up to the point of lead forming and insertion. Optional capacitors can be mounted to the package to maximize supply noise decoupling and increase board packing density. These capacitors attach directly to the internal package power and ground planes. This design minimizes resistance and inductance of the bond wire and package, both of which are critical in a transient radiation environment. All NC pins must be connected to either VDD, GND or an active driver to prevent charge build up in the radiation environment. (NC = no connect.)
36-Lead Flat Pack Pinout
GND VDD A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 NC VDD GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GND VDD W E A13 A8 A9 A11 G A10 S DQ7 DQ6 DQ5 DQ4 DQ3 VDD GND
28-Lead DIP Pinout
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Top View 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD W A13 A8 A9 A11 G A10 S DQ7 DQ6 DQ5 DQ4 DQ3
Top View
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36-Lead Flat Pack
H F Lead 1
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(2)
Lead 36
B (Width)
Lead 18 J M
(1)
Lead 19 E (Pitch)
A=.085 .010 B=.008 .002 C=.013 .004 D=.650 .010 E=.025 .002 F=.630 .007 G=.425 .004 H=1.490
J=.135 K=.080 L=.020 M=.285 N=.100 P=.040 Q=.130 R=.260
QML (USA) Date Code
D
G
A
Notes: 1) Part mark per device specification.
C
2) "QML" may not be required per device specification. 3) Dimensions are in inches. 4) Lead width: .008 .002. 5) Lead height: .006 .002. 6) Unless otherwise specified, all
P K VDD GND N Q R GND VDD GND VDD VDD GND L
tolerances are .005".
Lead 1 Indicator
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36-Lead Flat Pack with Pedestal Package
H F Lead 1 Lead 36
(2)
B
A=.137 .010 B=.008 .002 C=.013 .004 D=.650 .010 E=.025 .002 F=.630 .007 G=.425 .004 Notes:
H=1.490 J=.135 K=.450 L=.285
QML (USA) Date Code
D
G
Lead 18 J L
(1)
Lead 19 E
1) Part mark per device specification.
A K C
2) "QML" may not be required per device specification. 3) Dimensions are in inches. 4) Lead width: .008 .002.
VDD GND
5) Lead height: .006 .002. 6) Unless otherwise specified, all tolerances are .005".
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Lead 1 Indicator
VDD
28-Lead DIP
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For 28-Lead DIP description, see MIL-STD-1835, type CDIP2-T28, configuration C, dimensions D-10.
Ordering Information
32K x 8 CMOS Memory Device *Part Number 167A690 32K x 8 TTL Memory Device *Part Number 182A934
-
X X
Y Y
Z Z
X Package Designation 1 = 36-Lead FP 2 = 36-Lead FPP 3 = 28-Lead DIP
Y Speed Designation 3 = 30 ns 4 = 40 ns 6 = 60 ns
Z Screen Designation 1=QML VV 3=Engineering 4=QML VQ 5=QML QQ 7=Customer Specific
BAE SYSTEMS reserves the right to make changes to any products herein to improve reliability, function or design. BAE SYSTEMS does not assume liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.
BAE SYSTEMS An ISO 9001, AS9000, ISO 14001, and SEI CMM Level 4 Company 9300 Wellington Road, Manassas, VA 20110-4122 866-530-8104 http://www.iews.na.baesystems.com/space/ 0041_32K_8_SRAM.ppt
Cleared for Public Domain Release (c)2001 BAE SYSTEMS, All Rights Reserved
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BAE SYSTEMS * 9300 Wellington Road * Manassas, Virginia 20110-4122
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